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High Speed Interconnects.
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Chip-to-Chip Interconnects Design Challenges
Banpil High-Speed Metallic Chip-to-Chip Interconnects Solution
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High Speed Metallic Interconnect Applications
Chip-to-Chip Interconnects Design Challenges

The insatiable demand for bandwidth forces system designers to continue to strive to improve interconnects system performance. In order to maintain cost competitiveness, copper (metallic) based chip-to-chip interconnects remain an attractive proposition.

If asked to name their wish-list for realization of the optimum high speed copper interconnection system, system designers would invariably vote for infinite signal phase velocity, zero system power consumption, and high transmission bandwidth (over > 10 GHz). Unfortunately, we live in an imperfect world and these attributes are mutually exclusive. So, when asked to nominate one priority out of these three, the answer ultimately comes down to the ability of a copper connection system to cost-effectively deliver over 10 Gb/s signals from the active output of a transmitter to the active input of a receiver with zero bit rate errors, which need tremendously high bandwidth of the interconnects.

With well-defined design along with the usage of high cost low dispersion PCB material, the interconnects bandwidth can be increased. However, as the total cost of the finished PCB gets higher, this solution cannot be implemented in products.

The conventional FR4-PCB materials can barely meet today's data transfer rate requirements. Special circuits requiring high power and board layout techniques have been used to meet the critical signal path requirements. As data rates in excess of 3 Gb/s are beginning to increase for PCs, servers, multifunctional RF systems, game machines, communications and many consumer products, system designers have to come up with new design techniques to route such high-speed signals on the board. These techniques usually increase power budget, design time, and add undesirable costs to the products.

According to the ITRS (International Technology Roadmap for Semiconductors) technology roadmap, as shown in Fig. 1, the local clock speed in "on-chip" devices has increased from 1.8 GHz in 2000 to over 5 GHz by 2005. However, the chip-to-board (off-chip) speed can only be increased to 2 GHz, even by the year 2018 using conventional FR4-PCB technologies. This speed disparity between on-chip and off-chip signal speeds is projected based on the technology development trends.

Today, driving serial and parallel data at high speeds over copper on conventional PCB backplanes is becoming a major design bottleneck. As speed increases, signal losses, dispersion, and crosstalk also simultaneously increase, decreasing the signal-to-noise ratio. This limits the signal carrying capacity for a given channel length. To increase the signal-to-noise ratio, using today's conventional technology, special techniques such as packing signal lines, using pre-emphasize/equalizer in chips, or pins closer together are being used. Unfortunately, these efforts not only increase the system power budget 30 to 40%, but it also complicates design and add cost to achieve seamless inter-chip communication.

As chip pin count continues to rise, connecting signal pins from one chip to another can result in using very long signal traces. These limit the interconnect bandwidth further. The data rates on a PCB can never keep up with on-chip signal speeds if conventional metallic interconnect technology is used. To increase transmission distance, emphasis/equalizing techniques are added in both the transmitter and receiver side to recover the signal. However, an unfortunate side effect of this is that when boosting the appropriate frequencies, signal to noise ratios on the interconnect path remain constant resulting in increased crosstalk. This complicates the design and increases power consumption with the additional active components.

Banpil High-Speed Metallic Chip-to-Chip Interconnects Solution

It is highly desirable to develop a passive interconnect technology which will reduce greatly the disparity between on-chip and off-chip speeds without using the emphasis/ equalization techniques.

As chip technology continues to advance and system designers demand higher and higher speeds for signal interconnections, it has become very clear that today's metallic interconnect technologies are imposing too many limitations on maintaining signal integrity. These limitations frustrate end-users and designers, and severely impede the advances of the design of higher performance products. As a result, end-users are forced to develop their proprietary, sometimes brute force, interconnect technology for each new product. Board designers often find it a struggle to implement their design based on product specification using conventional board design technologies. Therefore, an innovative metallic interconnect technology is essential to remove today's limitations and to bridge the speed disparity between off-chip and on-chip high-speed data communication. BANPIL offers such kind of technology for current and future chip-to-chip communication design needs.

To fulfill these high-speed interconnect requirements and challenges, BANPIL has a patented technology, which enables high data rates across copper PCB and backplanes without the need for additional active components and time-consuming layout techniques. BANPIL technology uses conventional manufacturing process technology and FR4 material, allowing the implementation in today's and tomorrow's copper PCB and backplanes. Banpil's invention enable to increase the signal carrying capacity and supporting the reliable transmission of signal data in excess of 10 Gb/s across a copper FR4-PCB/ backplane without using pre-emphasis/equalization techniques.

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